Toshiba, a premier semiconductor manufacturer, has provided leading companies with Custom SoCs/ASICs for over three decades. Toshiba customers benefit from continuous collaboration from architectural design through production, access to an extensive portfolio of industry-standard and customizable IP, robust design methodologies and leadership in producing high-complexity and low-power SoC/ASICs with the industry's most advanced packaging technologies.

Toshiba brings a unique system-level perspective to its design capability. Utilizing its rich assets of leading technology, experience in product design in a wide variety of application areas and global presence. Toshiba can provide advanced, system level solutions to help its customers bring competitive products to market for networking, mobile, consumer, multimedia, storage and other applications.

System Solution

Toshiba works closely with top companies to deliver a complete solution that mitigates design risk with continuous collaboration from architectural design through production of Custom SoC and ASIC designs.

Reduce Risks Upfront with SoC "Virtual Prototyping"

Toshiba has developed a modern ASIC Virtual Prototyping system that allows for the concurrent co-design of a chip, package and system. By using the Toshiba chip/package/system co-development methodology, designers can optimize their ASICs for cost and performance, shorten development turnaround time and dramatically increase the likelihood of a successful design in first pass silicon compared to less sophisticated methods of co-design.

Chip packages

In essence, the Virtual Prototyping model signoff validates customers' design specifications by checking silicon and package integrity using a proven EDA toolset. In this signoff flow the package/device models and constraint information are read in from industry-standard third-party tools. The flow checks for the signal, IR, power and thermal integrity, in addition to ESD signoff, routability and bondability of the chosen package. This signoff is achieved within weeks of design start thereby eliminating many potential risks downstream.

This advance level of prototyping available from Toshiba provides its customers with a complete end-to-end ASIC design process that can often eliminate the need to work with third parties.

Toshiba offers "shuttle services" that enable you to create an ASIC prototype with low NRE costs. Instead of using a reticle for a single product, it is shared among multiple customers to split mask and wafer costs. Thus, shuttle services enable low-cost ASIC prototyping. The frequency of shuttles, the available chip size and sample quantities differ from technology to technology. The turnaround time varies depending on the process technologies, delivery form (wafer, chip or packaged sample) and quantities.

Toshiba serves a wide range of customer applications including networking, mobile, consumer, multimedia, storage and other applications.

Toshiba's comprehensive engineering support helps customers meet their Custom System-on-Chip and ASIC design specifications and development schedules at the lowest possible cost. Expert support is available from 2 U.S.-based Design Centers and additional locations for IP design.

For each Custom System-on-Chip and ASIC design program, a Toshiba engineering team is assembled to help customers create the best design based on system-chip architecture tradeoffs, silicon technology, cell libraries, IP, EDA tools, design flows, test, packaging, quality assurance and other criteria. Depending on each customer's own resources and skills, Toshiba engineers can work as expert consultants or provide access to Toshiba's sophisticated design tools.

Support and technical excellence are given the highest priority at Toshiba. Our design centers are strategically positioned around the world to support global customers by providing a high level of technical expertise in dealing with Toshiba ASIC technologies, design implementation and manufacturing methodologies. Our expert design centers are also available for design consultation.

• San Diego, California
• Boston (Marlborough), Massachusetts

Excellence in product design, processes, high-volume manufacturing techniques, and quality assurance are infused at every stage of production. This commitment to service before, during and after the design implementation is offered worldwide.

Global Design Centers

Toshiba supports a vast library of ready-to-use, pre- and post-tested IP for applications ranging from consumer and mobile to storage, multimedia and networking. Our library includes ARM processor cores, embedded memory, mixed-signal functions, system-level IP, and high-performance I/O for on-chip buses, chip-to-chip and chip-to-backplane interconnect, connectivity IP, PLLs and more.

To support additional IP requirements, Toshiba has partnered with a number of companies chosen because they provide proven, best-in-class IP and share Toshiba's commitment to reduce time to market, design risk and cost for its customers. Toshiba also works with key foundries, giving customers access to an even larger selection of differentiating IP.

• Industry cost-effective, embedded DRAM cores for low-power and high bandwidth up to 32 Mb/instance, 256-bits wide; uses trench cell technology for manufacturability.
• High-speed serial interfaces up to 12 Gbps and higher combined with digital IP cores.
• Mixed-signal cores include ADCs for converting data from sensors, DACs for driving image displays or audio, VGAs for analog signal compensation and PLLs.
• Pre-proven digital IP blocks for improved time to market, resource constraints and risk management.

Toshiba offers a wide variety of processors ranging from low-power microcontrollers such as ARM7 and Cortex-M3 to high-performance multiprocessors such as Cortex-A9 under a comprehensive licensing agreement with ARM. Toshiba also provides a wide variety of ARM peripheral cores.

Toshiba Roadmap ARM® Processor Cores

Toshiba is the leader in embedded DRAM technology and is currently shipping its 8th generation of product in high-volume production.

• High performance with fast data transfer rates due to wide on-chip memory buses.
• Much denser than SRAM
• Low power
• Low Soft Error Rates (SER)
• Multiple cores per chip.
• System architecture optimization and reduction of discrete components.
• Easy and effective testing with a direct-access test and DRAM BIST.
• High yield through redundancy in DRAM macros.
• Various types of DRAM macros with configurable depth and width.
• Trench process - one transistor DRAM cell structure utilizes trench process. The trench capacitor allows for a planar surface topology that enhances reliability without compromising logic performance.
• High bandwidth - freed from I/O restrictions, embedded DRAM cores provide high-memory bandwidth with asynchronous interface and a bus width selectable from 64-, 128- and 256 bits.
• Configurable Macros - DRAM macros are configurable in depth and width to suit particular application requirements.

Toshiba offers a large portfolio of mixed-signal cores that can be customized for specific applications, and the engineering expertise needed to ensure successful implementation

Toshiba offers a range of high-speed Serdes IP ranging from 0.622 to 12 Gbps.

Memory Interface IP

Toshiba offers popular memory Interface IP for your latest ASIC design.

• DDR2
• LPDDR21
• DDR32
• DDR32

Toshiba provides link, transport and physical layer IPs that implements popular connectivity IP.

Toshiba offers phase-locked loops (PLLs) and spread-spectrum clock generators (SSCGs) for various applications.

Toshiba offers A/D and D/A converters for various applications.

Toshiba provides IP that implements legacy communication protocols, as well as various memory card controller and cryptography IP.

The Toshiba design methodology integrates proven third-party EDA solutions with our internal silicon-proven design and manufacturing methodologies. This enables customers to increase their design productivity by reducing design time and iterations, and to achieve quality first-time right designs.

Implementation Methodology Overview

Toshiba offers a comprehensive ASIC implementation methodology which integrates the following capabilities throughout the entire architectural design to GDS design flow:

• RTL checking to ensure quality synthesis and
implementation
• Design constraints checking to drive quality
physical implementation
• Design prototyping to provide predictability and ensure design convergence for IR drop, congestion and timing closure feasibility from early to final netlist. This provides logic designers clear and early visibility in both chip architecture and performance before final P&R
• Built-in signal integrity avoidance, analysis and repair methodology
• Built-in DFM methodology to ensure high yield and quality parts

There are a number of factors to consider when selecting an optimal package configuration: I/O requirement, package footprint/form factor, thermal dissipation, electrical performance, and cost-to name a few. With ASICs now being introduced exceeding 100-million gates and operating at clock frequencies of 1 GHz and beyond, accurate package data and selection is critical. To meet system-level performance and density requirements, packages with better thermal and electrical characteristics that do not impact the performance of the die are needed.

New advanced packaging technologies, such as chip-on-chip, package-on-package and SCS (ASIC + DRAM) including TSV are currently available to meet the ever-increasing market demand for smaller size, reduced power, and high pin count designs. Toshiba also offers legacy packages including FC-BGA , PBGA, P-FBGA and QFP packages, as well as small WCSP and QFN packages.

Advance CMOS Fabs and Foundry Partners are the Cornerstone of Toshiba ASIC Business

Toshiba aggressively brings leading-edge CMOS processes and partners with top foundries for advanced ICs in 300mm manufacturing for its customers.

By leading the industry in producing high-performance system-level ICs in 90nm since 2003, plus production of 65nm and 40nm with 28nm process technologies underway, Toshiba is able to stay ahead of the yield curve. We're continually improving manufacturing processes to enhance performance, streamline time-to-revenue and reduce IC cost.

Your design benefits many ways, because we reliably deliver:

Our CMOS technology offering includes legacy processes from 0.8µm to 65nm and beyond, demonstrating Toshiba's deep support of customer specificity in product cycle needs. We also ensure full upgrade compatibility for meeting our customers' future goals. Current processes include:

	• ASIC 28nm • ASIC 40nm • ASIC 65nm • ASIC 0.90µm • ASIC 130 µm

Toshiba offers design implementation with deep experience in DFM, mixed-signal design, high-speed and low-power design, along with mask making and wafer fabrication, yield management and wafer test, bumping and assembly.