• Industry leader in producing high-performance system-level ICs in 65, 90 and 130 nm process
• New 300-mm wafer fab for production of Custom SoCs and foundry
• Flexible hand-off model starting from system block diagram to a traditional ASIC netlist
• Software can start just 2 months after block diagram using Toshiba software services and HW/SW co-development tools
• Eleven-layer copper CMOS technology
• Low-k dielectric and logic densities up to 400,000 gates/mm2
• Cost-effective embedded DRAM cores of less than 20mm sq for 32Mb
• Input/output cells support high-performance SerDes chip-to-chip interface applications as well as GigaEther, FibreChannel, Sonet and Wi-Fi.
• High-performance and high pin-count packages
• Commercial EDA design flow with signal integrity support and power analysis
• Local design support centers

To solve the challenge of engineering productivity, Toshiba's customers have cut their design cycles by months by using the Toshiba custom chip IP platform approach, which uses mix-and-match IP and a standardized bus structure.

For each Custom System-on-Chip and ASIC design program, a Toshiba engineering team is assembled to help customers create the best design based on system-chip architecture tradeoffs, silicon technology, cell libraries, IP, EDA tools, design flows, test, packaging, quality assurance and other criteria. Depending on each customer's own resources and skills, Toshiba engineers can work as expert consultants or provide access to Toshiba's sophisticated design tools. Toshiba can also deliver turnkey engineering services to facilitate a new or derivative design. To obtain further information regarding the products on this page, click here.

Quality and Reliability