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ASIC 65nm TC320
Ultra-High Density SoC and SiP Solutions for Ultra Low-power Applications

Toshiba's 65nm (TC320) family offers an ideal solution for multimedia and low-power portable applications, mobile phones and any other application where both high system integration and low-power consumption are important criteria. The 65nm (TC320) family is fabricated using the new CMOS5 process, which is a product of Toshiba's own process development.

As part of the ASIC design process, Toshiba's state-of the-art design environment is geared to shorten the development time for complex SiP designs incorporating high-speed interfaces. The environment features an unparalleled concurrent chip-package-system development methodology that takes into account the package and silicon characteristics during the planning and implementation phase of the product.

Advanced 65 nm Process Technology:
  • Utilizes embedded DRAM and tightly stacked semi-embedded DRAM capabilities.
  • Double the logic density, 15 to 20% reduction in gate delay, 30 to 50% reduction in power per gate.
  • Easy mixing of analog and application specific IP cores on the same chip.3
  • Multi-threshold process capability allows mixing of logic cells operating at different threshold voltages with an optional 1.0V core voltage.
  • Advanced optical proximity correction (OPC) technology bringing high-precision microfabrication.
  • Conditional clocked low-power flip-flops reduce both dynamic power consumption and leakage current.
  • Other low power technologies include dynamic frequency and voltage scaling, placement aware clock gating and placement aware clock tree synthesis, as well as the ability to accurately analyze the power consumption of the device.
  • Uses copper technology, low-k dielectric and the advanced 65nm (50nm drawn gate) CMOS process.
  • Up to eight levels of copper metal plus one level of aluminum interconnect.
  • A sophisticated IP library includes a full line of MIPS RISC processor cores and application-specific cores such as SATA, SAS, SerDes, PCI, USB, 1394, Ethernet, etc.
  • Advance flow design methodology tackles DFM issues and establishes high-precision timing closure -- typically enables a design to be achieved with only a few, simple layout ECOs.
Key Specifications-General Specifications
Process Technology 65-nm process, low-k interlayer dielectric
Gate Length 50 nm
Metal Wiring Up to 8-layer Cu plus 1-layer Al
Core Supply Voltage 1.2 V/1.0 V (option)
I/O Supply Voltage 1.8 V/2.5 V/3.3 V
Gate Density 800 kgates/mm2
Gate Delay 10.2 ps (LP), 7.8 ps (HS), 7.2 ps (VS)
Power Consumption 5.68 nW/MHz/gate (Fan-out = 0, CQIVX4)

 

Basic Libraries and SRAM/ROM
Core Cells A variety of synthesis-friendly core cells. High-speed library options with multiple thresholds
I/O Cells I/O cells in two shapes:
Standard width for general applications
Narrow width for high-pin-count applications
SRAM/ROM   Low-power library:
Single-edge-triggered high-density SRAM (up to 576 Kbits, up to 300 MHz)
Double-edge triggered middle-density SRAM (up to 288 Kbits, up to 350 MHz)
Single-port high-speed register file (up to 72 Kbits, up to 550 MHz)
Double-port register file (up to 72 Kbits, up to 400 MHz)
Triple-port register file (up to 9 Kbits, up to 500 MHz)
ROM (up to 1 Mbit, up to 200 MHz)
High-speed library:
Single-port edge-triggered high-density SRAM (up to 576 Kbits, up to 400 MHz)
Double-edge triggered middle-density SRAM (up to 288 Kbits, up to 500 MHz)
Single-port high-speed register file (up to 72 Kbits, up to 750 MHz)
Double-port register file (up to 72 Kbits, up to 550 MHz)
Triple-port register file (up to 9 Kbits, up to 650 MHz)
ROM (up to 1 Mbit, up to 300 MHz)

 

Basic Libraries and SRAM/ROM
Core Cells A variety of synthesis-friendly core cells. High-speed library options with multiple thresholds
I/O Cells I/O cells in two shapes:
Standard width for general applications
Narrow width for high-pin-count applications
SRAM/ROM   Low-power library:
Single-edge-triggered high-density SRAM (up to 576 Kbits, up to 300 MHz)
Double-edge triggered middle-density SRAM (up to 288 Kbits, up to 350 MHz)
Single-port high-speed register file (up to 72 Kbits, up to 550 MHz)
Double-port register file (up to 72 Kbits, up to 400 MHz)
Triple-port register file (up to 9 Kbits, up to 500 MHz)
ROM (up to 1 Mbit, up to 200 MHz)
High-speed library:
Single-port edge-triggered high-density SRAM (up to 576 Kbits, up to 400 MHz)
Double-edge triggered middle-density SRAM (up to 288 Kbits, up to 500 MHz)
Single-port high-speed register file (up to 72 Kbits, up to 750 MHz)
Double-port register file (up to 72 Kbits, up to 550 MHz)
Triple-port register file (up to 9 Kbits, up to 650 MHz)
ROM (up to 1 Mbit, up to 300 MHz)

 

DRAM Core
Mobile Library Clock Frequency 250 MHz (RL = 3)
Data Rate 8 GB/s
I/O Width 64/126/256 bits
Bit Range 4 Mbits to 32 Mbits
Standby Power 0.6 mW
Low-Power Library Clock Frequency 250 MHz (RL = 3)
Data Rate 8 GB/s
I/O Width 64/126/256 bits
Bit Range 4 Mbits to 32 Mbits
Standby Power 4.3 mW
High-Speed Library Clock Frequency 350 MHz (RL = 3)
Data Rate 11.2 GB/s
I/O Width 256 bits
Bit Range 8 Mbits to 32 Mbits
Standby Power 4.3 mW