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ASIC 40nm TC340

Process 40-nm node; low-k interconnect dielectrics and high-k gate dielectrics
Gate length 40 nm
Metal interconnect Up to 8-layer Cu + 1-layer Al
Core voltage Selectable from 1.1 V and 1.0 V.
I/O voltages 1.8 V/2.5 V/3.3 V
Gate density 2,100 kgates/mm2
Gate delay1 9.0 ps (High-speed type),12.0 ps (Low-power type)
Power dissipation2 0.59n W/MHz/gate
1 2-input NAND (X2); F/O = 2, wire load = 0
22-input NAND (X1); F/O = 1, wire load = 0, switching probability = 0.25