For actual design parameters, please contact Toshiba.
The TC260 family
of System-Level Integration (SLI) ASICs are designed for applications needing
the highest performance with the smallest die size. The TC260 employs the highest-density
interconnects, gates, memory, and I/O structures. The family includes TC260C/DC
Standard Cells for best density or TC260E/DE Embedded Arrays for fast turnaround
time. The 0.14µm drawn geometry is ideal for systems above 150MHz or 2Mgates
and those applications requiring the lowest power dissipation. Two technology
module options may also be employed, a Precision Analog Module for mixed-signal
applications and a performance Module for optimizing challenging timing paths.
Toshiba offers two types of embedded DRAM, one targeted for high-bandwidth,
the other for SRAM replacement applications. The embedded DRAM cores are based
on Toshiba's leading trench capacitor technology, which permits mixing of logic
and DRAM without degrading logic performance. Toshiba's IP library includes
a full line of MIPS®RISC and application-specific cores such as PCI, USB,
1394, AGP, SCSI, Fast Ethernet, etc. Toshiba's Timing-Driven Flow (TDF™)
design methodology is based on commercial EDA tools and ensures that timing
closure can be achieved typically with only a few simple ECOs.
