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ASIC 0.14μm-TC260
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The TC260 family of System-Level Integration (SLI) ASICs are designed for applications needing the performance with the smallest die size. The TC260 employs high-density interconnects, gates, memory, and I/O structures. The family includes TC260C/DC Standard Cells for best density or TC260E/DE Embedded Arrays for fast turnaround time. The 0.14µm drawn geometry is ideal for systems above 150MHz or 2Mgates and those applications requiring the lowest power dissipation. Two technology module options may also be employed, a Precision Analog Module for mixed-signal applications and a performance Module for optimizing challenging timing paths.

Toshiba offers two types of embedded DRAM, one targeted for high-bandwidth, the other for SRAM replacement applications. The embedded DRAM cores are based on Toshiba's leading trench capacitor technology, which permits mixing of logic and DRAM without degrading logic performance. Toshiba's IP library includes a full line of MIPS®RISC and application-specific cores such as PCI, USB, 1394, AGP, SCSI, Fast Ethernet, etc. Toshiba's Timing-Driven Flow (TDF™) design methodology is based on commercial EDA tools and ensures that timing closure can be achieved typically with only a few simple ECOs.



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ASIC 0.14μm-TC260
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Part Number / Datasheet
Usable Gate Density mm/sq
50µm TAB I/O Pads
Performance 2 input nand Fanout =1/ Fanout=2+wiring (ns)
Power Consumption (µW/gate/MHz)
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TC260C/DC 125 K 1568 0.04/0.06 ns 0.026 5W
TC260E/DE 72 K 1568 0.05/0.06 ns 0.036 5W

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