The TC280 family of System-Level Integration (SLI) ASICs are designed for
applications needing the highest performance with the smallest die size.
The TC280 employs high-density gates, memories, I/Os and interconnect
structures. This 0.11µm drawn gate length (0.13µm process geometry
ASIC family is ideal for systems above 200 MHz or 5Mgates. Three library
options for low power, high speed and very high speed may be mixed and
matched in designs to permit optimum performance with the smallest die size
and lowest power. Toshiba also offers two types of embedded DRAMs. The 250MHz
SD type is targeted for high-bandwidth, large-memory block applications and
the fast access FA type for SRAM replacement. These embedded DRAM cores are
based on Toshiba's production-proven trench capacitor technology, which
permits mixing of logic and DRAM without degrading logic performance.
Toshiba's IP library includes a full line of MIPS RISC processor cores and
application-specific cores such as 3.2G SerDes, PCI, USB, 1394, Ethernet, etc.
Toshiba's MegaGateTiming-Driven Flow design methodology includes advanced
wire-load models for synthesis, 3D capacitance extraction and signal
integrity analysis based around commercial EDA tools to establish
high-precision timing closure. Typically, this allows a design to be
achieved with only a few, simple layout ECOs.
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