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ASIC 90nm TC300

Related Information

The TC300 family of ASICs are designed for the highest-performance, next-generation products ranging from networking and server applications to digital multimedia devices that manage audio/video information and portable devices that require the lowest power consumption.

The TC300 family delivers approximately a 100% increase in gate integration, 20% increase is gate speed and a 50% reduction in power consumption compared to previous generation 130nm process technology. It's built on Toshiba's proven CMOS process technology (CMOS4) that permits easy mixing of mixed signal, DRAM and applications specific IP cores on the same chip. It supports two types of DRAM cores optimized for speed or density, Toshiba qualified primitives, I/Os and SRAMs, as well as a high-speed SerDes for a range of applications.

Advanced 90 nm Process Technology:
  • The process supports up to 11 layers of copper metal interconnect with logic densities up to 400,000 gates/mm2 or more and low-k dielectric.
  • A rapidly growing library of IP includes MIPS cores, memory, analog functions, networking IP and other application specific cores.
  • The Cell Libraries encompass a vast portfolio of compact, primitive cells optimized for automatic synthesis and multi-threshold voltage making it possible to select fast, ultra-fast or low-power consumption cells for best design results.
  • I/O cells include high-performance SerDes chip-to-chip interface applications for blackplane and line card products including GigaEther, FibreChannel, Sonet, and Wi-Fi (IEEE 1394b) applications.
  • Versatile SRAM cores support fast SRAM, high-integration SRAM, register files and high integration ROM
  • DRAM employs trench capacitor technology that permits mixing of logic and DRAM without degrading performance. Two kinds of cores are available:
  • SD Type DRAM for high bandwidth applications has a clock cycle of 300 MHz and a data transfer rate of a maximum 9.6 GB/sec
  • FA Type DRAM is optimized for fast access with a random access time of 6-8 ns and an I/O width of a maximum 288 bits
  • Range of package types for high performance SOCs including 200- to 2304-pin flip chip BGA; 109- to 256-pin PFBGA chip scale package and the 256- to 868-pin PBGA package with multi-layer structure and superior electrical characteristics.


General Product Specifications
Design Rule 90 nm, CMOS process, 11-layer Cu
Power Supply Core = 1.2 V; analog = 2.5V; I/O: 2.5 V/3.3 V (1.8-V option)
Gate Delay (F/O = 1, CIVX4 Gate) 14 ps (low-power library), 11 ps (high-speed library), 9.5 ps (very high-speed library)
  • Three types of transistors are available with different threshold voltages.
Gate Density 403 kgates/mm2
Power Dissipation 7 nW/MHz/gate (CIVX1 gate)