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Job Description
Req No: 3001
Location: San Jose, CA
Title: Principal Design Engineer - Hardware
Job Type: Full Time
Education Requirements:
 
Job Description:

Principal Design Engineer - Hardware

Candidate will work in Toshiba's exciting global team to Architect & Develop the next generation of PCIe & SAS SSD (solid state storage) SOCs.

As a key member of the Storage SoC Hardware development team, candidate will be responsible for creating SSD controller's architecture & participate in system modeling & design specification. Candidate will be working very closely with the design team to define the Hardware & Firmware architectures. As a part of the mission, architect will gather all the ASIC & F/W design requirements. This includes the assessment of in-house & 3rd party IPs for the SOC integration. Throughout the development phases, Architect will oversee the H/W & F/W design, will advise the designers & will help resolve any architectural & system issues.

EOE/AA M/F/D/V
 
Required Experience:
 

  • Perform detailed research and analysis of PCIe & SAS Enterprise SSD requirements
  • Participate in the SSD Controller ASIC HW & FW specification development
  • Oversee & Mentor the Flash controller design team in mapping the architecture concepts into RTL & Firmware implementation
  • Candidate will be in charge of both FE & BE architecture
  • Candidate will lead a team to develop both System Model &/or FPGA to check the concept's performance
  • Investigate controller requirements for Emerging memories such as NAND, MRAM & RRAM technologies
  • Investigate & participate in the assessment & development of emerging SSD technologies such as new ECCs (LDPC, BCH) CPUs, Host interfaces, DSP & high performance protocols
  • Architect automation HW to improve the Data & Command throughput
  • Investigate & analyze the landscape of the Silicon storage systems such as Flash matrix, DP engine, etc.
  • Minimum Skills & Experiences:

    Minimum of 10 years of experience in the following domains:

  • MSEE or PhD in Electrical Engineering or Computer Science
  • Strong experience in SSD controller H/W architecture & design
  • Experience in RTL design
  • Solid experience in PCIe & SAS interfacing & understand the I/O protocols
  • In-depth knowledge of NAND Flash memories & their operation
  • Understand various ECC codes
  •  
    Other Experience:
     

    Additional Candidate Experiences

  • Must have done multiple SOC tape outs
  • Must be knowledgeable in establishing the design data base structure, managing Libraries, IPs & Views
  • Should be fluent in writing scripts for synthesis, formality, netlist ECOs
  • Works closely with Japan & supplier & will supervise the toplevel RTL integration & netlist handoffs
  • Be able to manage Synthesis, Netlist, STA, clock tree, Pad ring & floor Plan.
  • You must apply to this position to be considered as an applicant for the role. Please do not just send your resume

     
     
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