Custom SoC World of Toshiba

3 U.S.-based Design/Support Centers • 15 Companywide

Leverage Our System and Silicon Expertise
for Your Next Design

90nm Leadership and Production-Volume
for Fastest Path to Advanced ICs

Toshiba, a world leader in Semiconductors, works closely with top companies to deliver a complete business-ready solution that mitigates design risk and ensures high-yield manufacturing of Custom System-on-Chip, ASIC designs and Foundry services.


	The Custom SoC World of Toshiba is the ultimate expression of advanced ICs. Welcome to our World. View >>

Custom System-on-Chip and ASIC Capabilities

Industry leader in producing high-performance system-level ICs in 90 and 130nm process

New 300-mm wafer fab for production of Custom SoCs and foundry

Flexible hand-off model starting from system block diagram to a traditional ASIC netlist

Eleven-layer copper for 90nm CMOS technology

Logic densities up to 400,000 gates/mm2

Cost-effective embedded DRAM cores of less than 20mm sq for 32Mb in 90nm

Input/output cells support high-performance, multi-protocol SerDes chip-to-chip interface applications as well as GigaEther, FibreChannel (2/4/8 Gigabit FibreChannel, SATA/SAS, USB 2.0, PCI Express), Sonet and Wi-Fi

High-performance and high pin-count packages

Local design support centers

Avoid Risks with SoC “Virtual Prototyping” Before They Start

Today’s ASICs typically demand high performance and low-power consumption in a small form factor. ASIC designers look to ever-shrinking semiconductor process technologies to help meet these constraints. However, the move to smaller process nodes presents a variety of design and economic challenges. Design rules grow at near exponential rates when moving to smaller process geometries, which in turn foster longer, riskier and more costly development cycles.

To address these issues, Toshiba has developed a modern ASIC Virtual Prototyping system that allows for the concurrent co-design of a chip, package and system. By using the Toshiba chip/package/system co-development methodology, designers can optimize their ASICs for cost and performance, shorten development turn around time and dramatically increase the likelihood of a successful design in first pass silicon compared to less sophisticated methods of co-design.


	Chip package system co-design flow View >>

In essence, the Virtual Prototyping model signoff validates customers’ design specifications by checking silicon and package integrity using a proven EDA toolset. In this signoff flow the package/device models and constraint information are read in from industry-standard third-party tools. The flow checks for the signal, IR, power and thermal integrity, in addition to ESD signoff, routability and bondability of the chosen package. This signoff is achieved within weeks of design start thereby eliminating many potential risks downstream.

As worldwide leader in integrated device manufacturing, Toshiba possesses the requisite design experience, tool and IP libraries and manufacturing expertise to give its ASIC customers a innovative design methodology that delivers quality results with minimized NRE. This advance level of prototyping available from Toshiba provides its customers with a complete end-to-end ASIC design process that can often eliminate the need to work with third parties.

Over 15 Million Chips in 90nm Since 2004

Toshiba holds a significant technological lead in delivering production-volume, high-yield 90-nanometer (nm) and 130nm custom System-on-Chips and ASICs. Early production of 65nm and co-development of 45 and 32nm process technologies are underway. With strict adherence to Design for Manufacturing (DFM) rules, the use of the latest yield prediction software, tools and manufacturing expertise—problems are solved early. This enables quick ramp up to high-yield production volumes and low defect densities.

Toshiba Custom System-on-Chips and ASICs incorporate pre- and post-tested IP including MIPS and ARM processor cores, memory, mixed-signal functions, high-speed serial interfaces (up to 8.0 Gbps), MPEG and more. Toshiba also holds a full-volume manufacturing lead in embedded DRAM technology for performance applications, or applications where availability of discrete DRAMs is uncertain.

Comprehensive Support

Toshiba's comprehensive engineering support helps customers meet their Custom System-on-Chip and ASIC design specifications and development schedules at the lowest possible cost. Expert support is available from 5 local Design Centers. However, in the case of extremely complex Custom System-on-Chip and ASIC designs, customers can call upon expertise from Toshiba's worldwide engineering network and facilities, including Research and Development Centers.

For each Custom System-on-Chip and ASIC design program, a Toshiba engineering team is assembled to help customers create the best design based on system-chip architecture tradeoffs, silicon technology, cell libraries, IP, EDA tools, design flows, test, packaging, quality assurance and other criteria. Depending on each customer's own resources and skills, Toshiba engineers can work as expert consultants or provide access to Toshiba's sophisticated design tools. Toshiba can also deliver turnkey engineering services to facilitate a new or derivative design.

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