15 Design/Support Centers Companywide

Support and technical excellence are given the highest priority at Toshiba. Our design centers are strategically positioned around the world to support global customers by providing a high level of technical expertise in dealing with Toshiba ASIC technologies, design implementation and manufacturing methodologies. Our expert design centers are also available for design consultation.

U.S.-based Design Centers

  • San Diego, California
  • Boston (Marlborough), Massachusetts
  • Minneapolis (Bloomington), Minnesota

Excellence in product design, processes, high-volume manufacturing techniques, and quality assurance are infused at every stage of production. This commitment to service before, during and after the design implementation is extended anywhere in the world.


Global Design Centers
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 Toshiba ASIC design centers provide global support

First-Time Right Designs Employ Advanced Tools and Methodology

Toshiba is focused on delivering predictable, yield-centric, first-time right ASICs and System-On-Chips. The Toshiba design methodology integrates proven third-party EDA solutions with our internal silicon-proven design and manufacturing methodologies. This enables customers to increase their design productivity by reducing design time and iterations, and to achieve quality first-time right designs.


Implementation Methodology Overview
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 First-time right designs employ advanced tools and methodology

Highlights

  • State-of-the-art, high quality, deep-submicron process technologies for a broad range of customer applications including wireless, automotive, digital consumer, networking and computing markets
  • EDA solutions integrate proven third-party EDA tools with internal silicon-proven design and manufacturing methodologies
  • A comprehensive ASIC implementation methodology which integrates the following capabilities throughout the entire RTL to GDS design flow:
    - RTL checking to ensure quality synthesis and
    implementation
    - Design constraints checking to drive quality
    physical implementation
    - Design prototyping to provide predictability and
    ensure design convergence for IR drop,
    congestion and timing closure feasibility from
    early to final netlist. This provides logic
    designers clear and early visibility in both chip
    architecture and performance before final P&R
    - Built-in signal integrity avoidance, analysis and
    repair methodology
    - Built-in DFM methodology to ensure high yield
    and quality parts

Number of 90nm chips produced by Toshiba since 2004.
Continuous collaboration before, during and after design implementation
Leading, proven third-party implementation tools
Collaboration from start to finish zoom image >>
Implementation tools
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Logic Design Tools

Synthesis

  • Synopsys Design Compiler
  • Magma Blast Create
  • Cadence RTL Complier

Delay calculation

  • Synopsys PrimeTime (sign-off for 90nm)
  • Toshiba NDM Delay Calculator (sign-off for .13um-.25um)

Simulation

  • Cadence Verilog-XL, NC-Verilog, NC-SIM, NC-VHDL
  • Synopsys VCS
  • Mentor/ModelSim

Static timing analysis

  • Synopsys PrimeTime (sign-off)

Power analysis

  • Sequence PowerTheater

Power optimization

  • Synopsys Power Compiler

Formal verification

  • Cadence Conformal LEC (Logic Equivalence Checking)
  • Synopsys Formality

Rules check

  • RTL
    - Atrena SpyGlass
  • DFT rules
    - Synopsys DFT Compiler, Tetramax
    - Atrenta SpyGlass (Toshiba rules)
  • Netlist rules
    - Toshiba NDM Dver Design Verifier

Constraints check

  • Magma Blast Logic
  • Atrenta SDC checker

DFT circuitry insertion

  • Scan
    - Synopsys DFT Compiler
    - Magma Blast Create w/Scan
  • Boundary scan, JTAG
    - Synopsys BSD Compiler
  • Memory BIST
    - Toshiba MemBIST
  • Logic BIST
    - Synopsys SOCBIST

ATPG test pattern generation

  • Synopsys TetraMAX
  • Mentor FastScan

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