TOSHIBA DEVELOPS PROMISING TECHNOLOGIES FOR 32NM GENERATION SYSTEM LSIs AND BEYOND

TOKYO, December 13, 2007 — Toshiba Corporation today announced that it has
achieved breakthroughs in three major basic technologies for 32nm generation system LSIs and beyond. The advances are a major advance in metal gate electrode; a new structure and process technology for low resistance contacts that reduce contact resistance; and a technology for improving performance by changing the surface orientation of the silicon substrate. The new breakthrough will pave the way to 32nm LSIs and improve process efficiencies.

The three technologies were introduced at the IEDM (International Electron Devices Meeting) conference held at Washington D.C., U.S.A., as major candidates for basic technologies for use in 32nm generation system LSIs and beyond. Toshiba will continue their development and optimization and aim for mass production in the first half of FY2010.

In developing the improved, new metal gate, Toshiba has realized a simplified manufacturing process technology that employs nickel silicide, a common material for both nMOS and pMOS transistors in a ratio of 1:3, respectively, and introduces an aluminum layer only in the nMOS gate.

For the low resistance contact, Toshiba employed a metal material in the source/ drain region, reducing contact resistance to a quarter in the nMOS side. The base electrode material is the same for both the nMOS and pMOS in pairs, and low-Schottky-barrier metal suitable for each type MOS transistor is segregated at interface of base material. The manufacturing process is simplified.c

System LSI integrates CMOS elements, nMOS transistors and pMOS transistors. Therefore an optimized process is required. These new two technologies enhance performance and also contribute to an efficient manufacturing process.

The technology for changing the surface orientation of the silicon substrate rests on the fact that using the (110) surface improves hole mobility as compared to the usual (100) surface. Toshiba found that both carrier mobility and gate capacitance increase in the (110) pMOS FETs, and demonstrated further improvement of drive current by 19% in a 32nm generation embedded-SiGe source/drain structure with 0.6% strain. In addition, the company found that the (110) pMOS FETs achieves a six-times faster processing speed in ideal conditions.

Background and Objectives


Challenges in 32nm generation system LSI development include minimizing electric resistance and improving performance. Achieving this is impossible without changes in basic materials and structures, and their optimization. Establishing the first metal gate technologies to be applied with 32nm generation, and minimizing contact resistance, and enhancing carrier mobility are imperative. Toshiba's achievements in solving these challenges bring other elemental advances into sight.

Each basic technology now needs to be optimized and careful verified.

Information in this press release, including product pricing and specifications, content of services and contact information, is current and believed to be accurate on the date of the announcement, but is subject to change without prior notice. Technical and application information contained here is subject to the most recent applicable Toshiba product specifications. In developing designs, please ensure that Toshiba products are used within specified operating ranges as set forth in the most recent Toshiba product specifications and the information set forth in Toshiba's "Handling Guide for Semiconductor Devices," or "Toshiba Semiconductor Reliability Handbook." This information is available at www.chips.toshiba.com, or from your TAEC representative.

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