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Pointers
and Pitfalls
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Power-Saving Clock-Gating Technique
is an Inseparable Part of SoC Design
In today’s higher performing SoCs, clock gating is increasingly becoming an
inseparable part of the system-on-chip design technique due to strict chip power requirements. In theory, clock-gated designs can achieve both lower power
consumption and improved timing performance compared to similar non-clock-gated designs. Typically, since not all circuits are in use all of the time, this variance in unused assets is an opportunity to reduce power dissipation.
The biggest power savings of clock gating will be for dataflow-intensive designs.
Collectively, the benefit of clock gating in portable electronics systems, for example, can be measured in longer battery life, as well as improved reliability and less costs associated with heat reduction.
Clock gating has an impact on static timing analysis (STA), clock tree synthesis (CTS), design-for-testability (DFT) and dynamic power analysis. Previously performed
manually by chip designers, the entire process of clock gating is now automated with a suite of design tools and methodologies offered by Toshiba. In customer designs, clock-gating techniques can significantly reduce the chip’s dynamic power compared to similar non-clock gated designs.
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Non-clock-gated vs. clock-gated register bank >>
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General implementation flow for clock-gated designs >>
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Clock Gating Pointers
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DO: At the RTL phase, before incorporating clock gating into the design, it is important to perform power simulation to confirm the power savings. Today’s power analysis tools can provide valuable clues to determine how much power can be saved by clock gating. |
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DO: When inserting clock-gating logic at the RTL, remember that most of today’s synthesis tools perform automatic clock gating without requiring any changes to the RTL code. |
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DO: If you don’t do clock gating during synthesis, remember that point tools are now available to insert it at the gate level. Please ask Toshiba ASIC design centers for details. |
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DO: Clock gating affects the design’s timing. The clock gates enable timing, which often becomes critical due to the clock tree skews. Remember to provide extra timing margins for the clock signals to the clock gates. |
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DO: Since clock-gating logic is bypassed during DFT, it is necessary to identify DFT enable signals before starting the clock-gate insertion process. |
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DO: The layout tool can manipulate clock gates for timing and power reasons. Depending on the capability of the layout tool, the clock-gate insertion strategy during synthesis may be different.
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At the synthesis stage, one may prepare the netlist with minimum amount of clock gates. This netlist will achieve the best power performance of the design. Then the layout tool can replicate (clone) the clock gates for realizing timing performance. |
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On the other hand, the layout netlist can be prepared with the maximum amount of clock gates. This netlist will achieve the highest timing performance. The layout tool can merge (de-clone) the clock gates to achieve lower power consumption as long as the timing is not violated. |
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Clock Gating Pitfalls
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DON’T: Use soft clock gates, which is a circuit described by a logic module of OR, LATCH, and AND gates. This is because the clock skew between the latch clock-pin and the clock signal going into the AND logic must be zero. Without special manual layout work, this is very hard to achieve. Therefore, always use the integrated clock gate (ICG) cells provided in the ASIC library. Toshiba ASIC technologies TC260/280/300/320 all provide ICG cells in many drive strengths. |
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DON’T: When performing static timing analysis, don’t forget to enable the clock-gate timing check mode, which is often set to disable as the default by some of the STA tools. |
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