Pointers and Pitfalls

Pointers & Pitfalls SoC Decision Tree Case Studies

Early Chip Sizing (Pre-sales) Carries High Financial and Technical Implications

Accurate and early estimation of chip size is critical to an overall project because it affects both financial as well as technical feasibility. If the die has too many pins for example, it may necessitate utilizing a package that is too large for the board. Or if it draws too much power, it may require airflow in a machine without fans. Toshiba’s obligation as an ASIC vendor is to help its customers obtain, as accurately as possible, a resolute picture of their end chip. We will review various tradeoffs to ensure our customer puts the right content in the die/package combination. Enabling them to see the implications of their various choices before design-in is vital in evaluating architectural and economic comparisons.

Sizing Falls into Two Categories
1. Pad-limited Sizing: In this type the number of pins required around the die determines the die size and the logic inside does not fill the entire available core area.

2. Core-limited Sizing: This is where the amount of logic on the inside dominates, thereby setting the die size. The I/O on this type of die may be widely spread, or large empty spaces may exist. The ideal die is a combination of the logic and the I/Os closely matching each other.

Point of Engagement
When is Toshiba typically asked to engage? Our contact is usually very early in the design stage, when a customer seeks quotation. This is generally at a point in the design cycle where design information is moderately defined, at best (unless it is an iteration of a previous function). That means Toshiba is heavily dependent upon information shared by the customer, which may not be totally defined. Customers can use the same methods to approximate their own die size.

Sizing Pointers: PAD Limited

DO: Figure the number of I/O pads needed for the design. Be sure to include bias cells or other special pads that may be required for any special I/O types that are used.

DO: Power calculation for the chip. Inaccuracies caused by rough power calculations can seriously lead to wrong tradeoffs for package and thus affect cost. Toshiba Design Centers generate such analysis, working closely with a customer at pre-sales stage of the design. All power components—static and dynamic leakages—are calculated to arrive at a manufacturable die/package combination.

DO: Select wire bond or flip chip based on cost, chip/package power dissipation, and pin count (will it require heat sink).

DO: Add sufficient core power and ground pins (wire bond case) to ensure <5% voltage drop from package power pin to package ground pin, relative to the center of the die.

DO: Add I/O power and ground pins at an average of 1 pair per 8 I/O.

DO: Ensure size of special cells (i.e. Serdes) is counted independent of pads count.

Sizing Pitfalls: PAD Limited

DON’T: Forget cut cells where bus isolation is required.

DON’T: Fully populate the corners. For a typical 50um wire bond chip the I/O can be placed at a density of 4 per 5 slots (200um). (In the corners assume half this as the cells must spread out. Use this number for the last 4 pads).

DON’T: For flip chip don’t plan on utilizing all slots as there are dead slots in the corners.

DON’T: Forget corner cells for sizing. (Assume the corner cell is the same height as the I/O cell. So double the height and add into die size).

DON’T: Assume that you could route all I/O in the corner of the package. There are a high density of balls and not enough routing resources. This forces many pins to be power and ground connections to planes.

DON’T: Put all your powers and grounds in the corner. They need to be evenly distributed around the die.

Sizing Pointers: Core Limited

It is harder for the customer to predict the size of their chip if it is Core Limited. Density achievable in the router is a key factor in sizing the core correctly.

Wire length can vary greatly with design style and logic content. Obviously if the wire length is short, then the area taken up by wire is small and vice versa. Toshiba Design Centers have successfully developed optimization techniques to reduce the impact of logic on the number of layers and overall density. Our Design Centers use a series of tools to help with size prediction. The following insights are for the DC.

DO: Ensure a complete list of RAMs and ROMs is received.

DO: Include special cells (core portion).

DO: Include redundancy for RAMs (fuses).

DO: Assume medium density for logic, unless you know the specific logic can route very densely based on past experience.

DO: Assume 20% extra logic to cover testability, buffering and optimization.

Sizing Pitfalls: Core Limited

DON’T: Assume that all portions of the core will achieve the same density.

DON’T: Assume that large macros can be abutted. Leave space for routing and power resources.

DON’T: Assume analog can be placed adjacent to each other. Give them a couple of hundred microns separation.

DON’T: Use areas of the die that have restricted access. Corner area is difficult to use if there are large I/O Phy macros on adjacent sides (see Figure 3). Figure 3

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