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Pointers
and Pitfalls
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High-Speed I/O Design Considerations in Low-Cost Packaging Applications
The use of high-speed I/O in almost every ASIC design requires careful design consideration to avoid issues with power and ground noise and coupling between sensitive signals. Spacing constraints and the desire for very dense designs can lead to signal integrity issues within the package. Timing problems due to crosstalk and simultaneous switching outputs will also become more prevalent in packages with high-speed I/O.
Manufacturing yield and adherence to industry-standard specifications can be maximized over the operating environment of a packaged product through simulation and analysis, with respect to the timing budget. Toshiba utilizes numerous extraction and simulation tools and provides the essential mixed-signal design service resources to analyze signal integrity issues prior to tape out.
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FC-400 I/O simulated vs. measured results >>
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HSTL800 I/O simulated vs. measured results >>
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High-Speed I/O Pointers
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DO: Consider differences between packages, either 5 row or 6 row, when determining package substrate routing resources. Better spacing is achieved with fewer row designs. |
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DO: Consider synchronous single-ended I/O to be more sensitive to simultaneous switching outputs requiring more on-die bypass capacitance per I/O. |
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DO: Specify adequate power and ground package pins while adding multiple, plated through-hole connections from package substrate planes to pins. Power and grounds should be evenly spaced in the package periphery. |
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DO: Discuss with Toshiba Engineering any signal integrity analysis that is to be done to yield design-timing margin. Prepare to define the link from the near end ASIC to far end receiver and visa-versa. |
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DO: Consider placing high-speed I/O in the center of die and package to minimize routing
to corners, where the package substrate etch would be longer and require longer bond wires. |
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High-Speed I/O Pitfalls
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DON’T: Use 100% of signal I/Os with minimum power and ground assignments if there is numerous high-speed single-ended I/Os in the design. Extra power and ground package pins free-up routing resources within the package substrate for extra spacing. |
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DON’T: Route high-speed I/O into corners of the die or package. |
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DON’T: Concentrate all high-speed I/O on one edge of the die. This is important for designs with numerous asynchronous I/O such as SATA/SAS or Fiber Channel switches. |
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DON’T: Concentrate power and ground pins in the corners of the die or package.
Too many in a single spot appear as a single pin. |
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