Pointers and Pitfalls

Pointers & Pitfalls SoC Decision Tree Case Studies

Power Management Poses a Critical Design Constraint
in the SoC World of Consumer Applications

Power management—and power-based differentiation—is fast becoming one of the most critical design constraints in the world of IC designers. The challenge of designing chips with optimum energy density and power consumption threatens to increase design time and, therefore, time-to-market. Engineers need to routinely apply sophisticated low-power design methods that can address the rising impact of power problems occurring in nanometer designs at 130nm and below, as well as in portable electronic devices and large complex digital ICs.

Power consequences occur at every stage of the design process, but addressing them early on will result in greater impact. Since attempts to reduce power can affect performance attributes such as timing, area, testability and signal integrity, understanding requirements for example of a multimode system that warrants a multi-core processor will drive technique.

Toshiba can provide low-power design flow from the architecture exploration to physical design implementation, using cutting-edge EDA tools, models and processes. Toshiba offers multiple libraries for power and performance tradeoff, as well as special cells to meet customer low-power design requirements.

Managing power at each stage of the design. >>

Address power management early. >>

Power Management Pointers

DO: Consider critical hardware and software tradeoffs between chip power and system performance.

DO: Select reasonable system frequency, I/O loading conditions and appropriate process technology based on total chip power.

DO: Consider module size and interface with other logic to decide setting module to idle mode by stopping the clock, to sleep mode by blocking the input signals, or totally turn the power off where possible.

DO: Discuss with Toshiba Engineering for available solutions such as multi-voltage core supply options, multi-threshold cell libraries, power islands techniques, and special cells to ensure minimum power consumption for your application.

DO: Consider splitting the large memories because it will help to reduce the power for the chip. However, be aware of the increase in the total megacell size and difficulty in physical implementation.

DO: Use clock-gating cell methodology for power saving. Testability should be considered while using gated-clock cell. Limiting clock insertion delay can reduce the clock tree power.

DO: Balance the datapath and operator isolation as this helps reduce the glitches on data transportation.

DO: Consider IR drop-in timing analysis because the timing delays are significantly affected in technologies at 130nm and below. Final power analysis should cover not only the functional mode, but also the test mode.

Power Management Pitfalls

DON'T: Over-constrain design due to excessive power consumption.

DON'T: Use high-speed versions of libraries for random logic and SRAMs, where possible.

DON'T: Forget to gate the clocks for RAMs to save power.

DON'T: Insert clock gating cells and level shift cells manually. Let the synthesis and automation tools select multi-threshold cells and handle insertion of the cells.

DON'T: Forget to plan, estimate, and optimize the design for power at every possible stage of the design process. At some stages, estimation can be easy using design automation tools. In some other stages, you have to rely on approximations and assumptions.

DON'T: Overuse decoupling capacitors as this does not help low-power design.

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