|
 |
Custom SoC / ASIC Resources
These resources are available to assist in the development of your Toshiba Custom SoC design. A partnership with Toshiba brings you not only the performance of our ASICs, but also comprehensive design support, an Open EDA strategy, quick prototype turnaround, steep production ramp-up, and proven high-volume manufacturing capacity in 90nm.
|
|
Product Guides
- CMOS ASIC:
- 18-page guide to Toshiba ASIC product lines, System ASICs, Megacells, Cell availability, packaging and more.
- Packaging:
- 18-page guide to optimal package solutions for customer systems of all kinds. Toshiba has applied technical developments to package manufacture to achieve the following six goals: miniaturization, light weight, slim profile, high pin count, high speed and excellent heat dissipation.
Product Briefs
- NEW "ARM Product Brief"
-Toshiba takes a system-level approach to designing with ARM cores.
- NEW "Virtual Prototyping for a Custom SoC"
- Overview of key features and benefits of the Toshiba Virtual Prototyping system that allows for concurrent design of chip/package/system.
- UPDATED "Complete Custom System-on-Chip (SoC)
Business Solution"
- Short overview of key features and benefits inherent with Toshiba "Custom SoC engagement.
- UPDATED "Multi-protocol, High-speed SERDES I/O Core"
- A
low-risk, silicon-proven solution designed in the Toshiba 90 nm process for smallest footprint and reduced cost.
White Papers
- "How OEMs Can Enhance Market Leverage and Knowledge Leadership by Leveraging IDMs"
- Identifying and evaluating the tradeoffs between purchasing off-the-shelf components or choosing the custom SoC option.
- NEW "Toshiba RFCMOS ASIC: A Methodology for Successful RFCMOS SoC Implementation"
- Increased demand for RFCMOS designs is driven by high-bandwidth, portable applications
- The Toshiba RFCMOS ASIC methodology reduces the costs associated with RFCMOS design
|
[ 1.07MB / PDF ]
[ 2MB / PDF ]
[ 247KB / PDF ]
[ 247KB / PDF ]
[ 160KB / PDF ]
[ 220KB / PDF ]
[ 261KB / PDF ]
[ 304KB / PDF ]
|
Pointers and Pitfalls: Engineering and Design Insights |
- NEW "Power-Saving Clock-Gating Technique
is an Inseparable Part of SoC Design"
- NEW "Impact of Multiple-Voltage Domain (Multi-VDD)
Design Implementation on Large, Complex SoCs"
- "Early Chip Sizing (Pre-sales) Carries High Financial and
Technical Implications"
- "High-Speed I/O Design Considerations in Low-Cost Packaging Applications"
- "Power Management Poses a Critical Design Constraint
in the SoC World of Consumer Applications"
|
[ HTML | PDF ]
[ HTML | PDF ]
[ HTML | PDF ]
[ HTML | PDF ]
[ HTML | PDF ]
|
Case Studies: Influencing Timelines and Bottom Lines |
- NEW "Toshiba Foundry Expertise and Ultra Low-Power 130 nm Process Help Global Locate Release Advanced A-GPS
Chipset Early"
- "iStor Networks Finds the Toshiba SoC World a Perfect Environmentto Power GigaStorATX Storage Controller for SAN Over IP"
|
[ HTML | PDF ]
[ HTML | PDF ]
|
|
|
Expand
Collapse