Toshiba Introduces Double Data Rate Toggle Mode NAND In MLC And SLC Configurations

IRVINE, Calif., August 11, 2010— Toshiba America Electronic Components, Inc ., (TAEC)* is introducing 32nm double data rate Toggle Mode NAND, in multi-level cell (MLC) versions with densities of 64Gb¹, 128Gb and 256Gb and single-level cell (SLC) versions with densities of 32Gb, 64Gb and 128Gb. Toggle Mode NAND features a faster interface than conventional or “legacy” asynchronous NAND memory with lower power consumption than competing synchronous DDR NAND product offerings.

Toshiba DDR Toggle Mode 1.0 NAND has a fast interface rated at 133 megatransfers/second² (MT/s), compared to 40MT/s for legacy SLC single data rate NAND, which makes it suitable for high performance solid state storage applications including enterprise storage. Since it uses an asynchronous interface similar to that used in conventional NAND, the Toshiba DDR Toggle Mode NAND requires no clock signal, which means that it uses less power and has a simpler system design compared to competing synchronous NAND alternatives. The DDR interface in Toggle Mode NAND uses a Bidirectional DQS to generate input/output signals (I/Os) using the rising and falling edge of the write erase signal. Toggle Mode NAND also has on-die termination to help achieve less crosstalk.

Scalability to future high-frequency operation is enabled as a result of the bi-directional data signal. Toshiba recently announced a commitment to a new standard for the most advanced high-performance NAND flash memory, a DDR NAND flash with a 400Mbps³ interface. This next generation Toggle Mode DDR NAND 2.0 is targeted to provide a three-fold increase in interface speed over Toggle DDR 1.0 and a ten-fold increase over the 40Mbps single data rate NAND in widespread use today.

Toshiba Toggle Mode NAND supports common legacy NAND commands including basic, multi-plane and cache operations.

Toshiba 32nm Toggle Mode Specifications

Type	Density	Configuration	Page/Block Size	Package	Vcc	VccQ
SLC	32Gb (4GB)⁴	2st/2CE	8kB/1MB	132 BGA	2.7 - 3.6	1.8
						3.3
	64Gb (8GB)	4st/4CE	8kB/1MB	132 BGA	2.7 - 3.6	1.8
						3.3
	128Gb (16GB)	8st/4CE	8kB/1MB	132 BGA	2.7 - 3.6	1.8
						3.3
MLC	64Gb (8GB)	2st/2CE	8kB/1MB	132 BGA	2.7 – 3.6	1.8
						3.3
	128Gb (16GB)	4st/4CE	8kB/1MB	132 BGA	2.7 - 3.6	1.8
						3.3
	256Gb (32GB)	8st/4CE	8kB/1MB	132 BGA	2.7 – 3.6	1.8
						3.3

*About Toshiba Corp. and TAEC

Through proven commitment, lasting relationships and advanced, reliable electronic components, Toshiba enables its customers to create market-leading designs. Toshiba is the heartbeat within product breakthroughs from OEMs, ODMs, CMs, distributors and fabless chip companies worldwide. A committed electronic components leader, Toshiba designs and manufactures high-quality flash memory -based storage solutions, discrete devices , displays , advanced materials, medical tubes , custom SoCs/ASICs , digital multimedia and imaging products , microcontrollers and wireless components that make possible today's leading cell phones, MP3 players, cameras, medical devices, automotive electronics and more.

Toshiba America Electronic Components, Inc. is an independent operating company owned by Toshiba America, Inc., a subsidiary of Toshiba Corporation, Japan's largest semiconductor manufacturer and the world's third largest semiconductor manufacturer ( Gartner, 2009 WW Semiconductor Revenue, April 2010). Toshiba was founded in 1875, and today operates a global network of more than 740 companies, with 204,000 employees worldwide and annual sales surpassing $68 billion.

For additional company and product information, please visit http://www.toshiba.com/taec/. For more information on TAEC memory products, visit memory.toshiba.com

¹When used herein in relation to memory density, gigabit and/or Gbit means 1,024x1,024x1,024 = 1,073,741,824 bits. Usable capacity will be significantly less due to the need for overhead data areas, formatting, bad blocks, and other constraints. For details, please refer to specifications.

²Megatransfers (MT) per second refer to the number of data transfers (or data samples) captured per second, with each sample occurring at the clock edge. In a double data rate system, the data is transferred on both the rising and falling edge of the clock signal. For purposes of measuring data transfers in this context, 1 Megatransfer equals 1,000,000 transfers per second. Actual data transfer speed may vary depending on the device, read and write conditions, and file size.

³Mbps, or megabit per second. For purposes of measuring read and write speed in this context, 1 megabit or Mb = 1,000,000 bits. Maximum read and write speed may vary depending on the device, read and write conditions, and file size.

⁴ When used herein in relation to memory density, gigabyte and/or GB means 1,024x1,024x1,024 = 1,073,741,824 bytes. Usable capacity will be significantly less due to the need for overhead data areas, formatting, bad blocks, and other constraints. For details, please refer to specifications.

Information in this press release, including product pricing and specifications, content of services and contact information, is current and believed to be accurate on the date of the announcement, but is subject to change without prior notice. Technical and application information contained here is subject to the most recent applicable Toshiba product specifications. In developing designs, please ensure that Toshiba products are used within specified operating ranges as set forth in the most recent Toshiba product specifications and the information set forth in Toshiba;’s "Handling Guide for Semiconductor Devices," or "Toshiba Semiconductor Reliability Handbook." This information is available at www.chips.toshiba.com, or from your TAEC representative.

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